1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor integrated circuits, and more specifically to a method for manufacturing integrated circuits having multilayers of metal interconnect lines.
2. Description of the Prior Art
By increasing the density of components in an integrated circuit, it is necessary to use multiple layers to fabricate the various components, and contacts between the layers to connect one layer to another. Fabricating the contacts and multiple layers, however, results in the creation of hills and valleys on the surface of the device. Those skilled in the art will recognize it is difficult to get upper interconnect layers to maintain constant cross sections when crossing over uneven topography. This can lead to step coverage problems, such as voids in the metal interconnect lines and contacts. Step coverage problems can also result in the metal interconnect lines having a higher current density. These defects can cause electromigration or other related device failure mechanisms.
Therefore, it would be desirable to provide a method for fabricating integrated circuits which alleviates step coverage problems and presents a planarized topography. It is also desirable that such a method not significantly increase the complexity of the manufacturing process.